To communicate timing performance targets to electronic design automation (EDA) tools for a field programmable gate array (FPGA), a designer specifies timing constraints, such as, clock period constraints, input/output setup times (IO TSETUP), and input/output hold times (IO THOLD). Based on these timing constraints, these EDA tools attempt to generate design implementations which satisfy the designer's performance targets. The EDA tools also report whether the specified timing constraints have been satisfied so the designer can take measures, if necessary, to try to improve the design implementation. For example, the designer may change a set of EDA tool settings on the EDA tool.
Usually, the FPGA includes multiple registers including a source register and a destination register, and at least one clock source. The source and destination registers are connected to each other via a register-to-register path. A minimum clock period for the register-to-register path in the design is primarily a function of three delays including a maximum path delay between the source register and the destination register, a maximum path delay from the clock to the source register, and a minimum path delay from the clock to the destination register. A difference between the maximum path delay from the clock to the source register and the minimum path delay from the clock to the destination register is referred to as clock skew for the two respective registers. Minimizing the maximum path delay between the source and destination registers to minimize the clock period is the focus of most EDA optimization.
The EDA tools often ignore the clock skew between the registers during optimization because clock signals are distributed on low-skew routing resources or networks. However, some routing resources or networks may not have low skew in which case the clock skew cannot be ignored.
Further, the designer manually may repair design implementations of the FPGA by skewing clock signals to achieve a desired timing margin. This can be a difficult and time consuming process. The designer may have to figure out a desirable skew solution that can be tricky and tedious with ever growing design size of the FPGA. Also, the designer may have to figure out how to implement that skew solution using the available FPGA hardware. That can also be tricky given the complexity of the clocking logic topologies common in the FPGA. Finally, the designer may manually insert logic into the FPGA, and adjust placement and/or routing of the design implementation, which can also be very challenging given FPGA complexity and growing design sizes.